The DNx-PL-820 are user programmable FPGAboards. The board allows an FPGA programmer to add customFPGA functionality to the DNx family and the various platforms itsupports.
The DNx-PL-820 is a two board, base/daughter card product. Thebottom board (left in a DNR RACK) includes a Cyclone II FPGA whilethe upper board (right in the RACK) provides a MAX 10 FPGA. TheCyclone board is used exclusively as the interface between the DNxbus and the MAX 10 FPGA chip. The MAX 10 chip is fully programmableby the user using popular Altera development tools, including theembedded Nios II processor.
The MAX 10 board allows user developed FPGA applications to beinstalled and run on the board. 104 GPIO pins are brought out fromthe MAX 10 FPGA and are available for connections to user I/O. 51bits are provided on the Cyclone board’s I/O connector while 53 areprovided on the MAX 10 board connector.
The MAX 10 has a variety of unique and powerful features that makeit an ideal choice as a custom FPGA target. Included in these featuresis a unique, instant-on capability that allows the MAX 10 applicationto begin running immediately, without regard to whether the Cubeor RACKtangle has completed its boot-up process. The MAX 10 alsosupports user and dual configuration FLASH, DSP blocks and Nios IIembedded processor functionality.
The MAX 10 chip may be programmed by a JTAG interface that isbrought out to the I/O connector or by the DNA backplane (viathe Cyclone chip) by a utility provided by UEI. A set of jumpers onthe board allows the JTAG interface to be disabled when securityconcerns mandates it. Security is further provided by the MAX 10’simplementation of a nonvolatile security key. Without the key theMAX 10’s FPGA image cannot be read or written.
The unit is shipped with an FPGA Image installed in the MAX 10 thatsimply sets each I/O pin as a general purpose DIO pin. The UEI API canthen set each I/O bit independently as input or output. The PL-820includes a test adaptor that connects the I/O pins from the Cyclone IIboard’s I/O connector to the MAX 10 board’s I/O connector (recall allGPIO pins are connected to the MAX 10). This allows each I/O pin tobe exercised as both input and output and allows a quick self-test toensure all I/O pins are fully functional
The Cyclone chip communications with the MAX 10 utilizing two, fullyprogrammable SPI interfaces. An fixed SSI interface is also included but itis currently reserved for system level configuration purposes. The Cyclonechip also provides two programmable clock signals to the MAX 10.
Unlike most DNx series boards, the DNx-PL-820 is not isolated from theDNx chassis. However, all I/O pins are protected with 165 Ohm seriesresistors and low capacitance bidirectional protection diodes.
Software for the DNx-PL-820 includes a high level, easy to use interfacethat allows you to configure and use the two SPI ports that connect theCyclone and MAX 10 chips. It also allow you to program the MAX 10 chipfrom your host PC through the Cube/RACK’s Ethernet port. Finally thesoftware provided allows you to control/monitor all the GPIO includedon the Cyclone II board (and the MAX 10 in its default state). The APIprovided is compatible with Windows, Linux, VxWorks, QNX and more.