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Intro | Applications | Quad-Core CPU | Additional Features | Linux Systems | Zynq vs SoloX ARM | Software | TSN | Security | More Info

IDEAL FOR EMBEDDED CONTROL & MONITORING SOLUTIONS

  • Available on all UEI’s Programmable Automation Controller (UEIPAC) systems.
  • 10x the processing power of UEI’s prior CPU.
  • 100x real-time performance increase via FPGA.
  • 3 GigE Ethernet ports, supports IEEE-1588.
    • Quad-core ARM cortex - A53, 64-bit processor combined with a user programmable Xilinx FPGA.
    • 4 GByte, 64-bit DDR, 8 GByte FLASH
  • Dedicated ARM Mali GPU with the full HD video support.
  • M.2 slot for NVMe SS drives up to 512 GByte.
  • TSN Support
  • Cyber Security (NIST SP 800-213A)
  • Compatible with UEI's entire product line.
  • 10-Year Availability Guarantee and 3-Year Standard Hardware Warranty.

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Zynq and Your Applications

The new Zynq UltraScale+ based CPU offers up to a 10x increase in CPU performance over previous CPUs. When utilizing the built-in Xilinx FPGA, an increase in real-time performance up to 100x is possible.

The new CPU joins the currently supported Freescale MPC5200/8347 and SoloX based CPUs in the UEIPAC family and all are covered by UEI’s powerful 10-year availability guarantee. The initial release supports the Linux operating systems while VxWorks and PIKE OS support is expected in the future.

The UEIPAC offers an unprecedented combination of flexibility, high performance, low cost and small controller. The unit is an ideal solution in a wide variety of measurement and control applications. The UEIPAC is also an ideal solution for embedded DAQ applications, allowing systems to operate without the cost or additional space required by an external host computer.

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ENHANCED QUAD-CORE CPU PERFORMANCE

The latest (fifth) Generation CPU uses the Xilinx Zynq® UltraScale+ device. A major advantage of the Zynq series is its combination of a multicore CPU with a Xilinx FPGA. In particular, the Zynq SoC provides a modern, quad-core ARM Cortex -A53 MPCore CPU running at up to 1.2GHz with 4GB of DDR4, 64-bit RAM. The CPU is based on the Zynq ZU3EG series chip and offers up to 192k logic cells. (Please contact the factory for more details on the capabilities of the Xilinx FPGA and the availability of higher density UltraScale+ devices).

The CPU includes three IEEE-1588 compliant GigE Ethernet ports. A DP (display port) supports full HD graphics (1080p). 8 GByte eMMC FLASH drive included on the board. For larger disk drive needs, a PCIe M.2 slot allows for the installation of 2242 or 2260 series NVMe cards, which are currently available in sizes up to 512 GByte. An external Synch port is provided, along with a USB 3.0/2.0 port. An RS-232 diagnostic port rounds out the I/O connectivity of the CPU board.

ADVANTAGES OF QUAD-CORE

  • Symmetric Multiprocessing (SMP)
  • CPU Affinity
    • Assign thread/process to run on specific core(s)
    • Leave leftover cores to handle other tasks
  • Example: Acquiring data and writing to file
    • CPU intensive may be acquiring data, assign two cores for DAQ, one core for file I/O
    • Data pumped smoothly to file
  • Heterogenous computing
    • FPGA can do some heavy lifting

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ADDITIONAL FEATURES OF THE ZYNQ ULTRASCALE+ BASED CPU

  • Built-in DP (Display Port) (4k) support
  • USB 3.0/2.0 interface
  • Direct support of DNx series sync port
  • Extensive diagnostics including power supply and temperature monitoring
  • Serial diagnostic port
  • All standard UEI chassis environmental specifications
  • 9-36 VDC power (universal AC adaptor also included)
  • Low power: 12W typical, <18W in most configurations
  • TSN Support
  • Cyber Security (NIST SP 800-213A)

The Zynq UltraScale+ version of the UEIPAC supports Linux OS with future support for VxWorks and PIKE OS expected.

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LINUX SYSTEMS

  • Uses Yocto Linux distribution: Petalinux 2020.2 Yocto (Zeus), Linux kernel 5.4.0, PREEMPT_RT patch for real-time support
  • Program in standard C/C++ or Python
  • Eclipse IDE support
  • Develop on Linux PC or Windows PC environment

The UEIPAC is supported by all UEI DNA/DNR/DNF series chassis. There are currently over 80 different I/O boards available, including analog input (with up to 24 bit resolution), analog output, digital I/O, MIL-STD-1553, AFDX, ARINC 429/453/708, Serial and CAN communications, counter/timer, quadrature encoder input and more. With this many different I/O boards available, there is sure to be a configuration perfect for your application.

The Zynq UltraScale+ based UEIPAC is an ideal high performance embedded controller where high-speed real-time analysis and decisions are required. The unit’s UEISIM deployment is also an ideal hardware target for Simulink based I/O applications where high speed, ruggedness and high reliability are required.

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ZYNQ BENCHMARKS VS SOLOX/ARM

Buffer Read/WriteUDP Packets
4x over SoloX/ARMUp to 8x throughput over SoloX/ARM.
  • SoloX: ~2,700 packets/s
  • Zynq: ~30,000 packets/s
ARINC-429 LoggingMemory

3x over SoloX/ARM, 192 channels

  • Zynq also has room to spare
  • SoloX/ARM: 1GB RAM
  • Zynq: 4GB RAM
CoresTested CPU Speeds
  • SoloX/ARM: Single Core, NXP i.MX6 1GHz
  • Zynq: Quad Core, Xilinx Zynq UltraScale+ 1.2GHz
  • Zynq provides 4x+ computing power above SoloX/ARM.
  • Multiple cores allows for better control over multi-threading application (tasks can be spread among cores)

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SOFTWARE BACKGROUND

  • PentaLinux 2020.2
  • Wrapper around Yocto Zeus
  • Builds
    • Bootable image (QSPI)
    • Linux RT kernel and rfs (eMMC)
    • SDK with wealth of tools
  • Logic for UEI bus, as well as Ethernet, PTP and TSN
  • Incorporate Logic IP alongside ours (TBD)


What is Vivado BSP?

A codeset for customers to add deployment-specific FPGA functionality

  • A set of TCL scripts to create Vivado project
  • UEI IP in the form of complied product to control PDNA bus and UEI devices
  • Block diagram, editable by the customer
  • Customer can add their own IP to UEI product and build bitstream for FPGA reconfiguration
  • A set of meta-layers for Petalinux to build Linux kernel with support of UEI and customer IPs

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TIME SENSITIVE NETWORKING (TSN)

Normal networks send packets without regard to timing considerations. TSN network technology allows you to have deterministic and reliable networking capable of running critical systems reliably and determinisitically. It doesn't mean super-fast (throughput) or super-slow (latency). It means being definitely and unequivocally characterized. A deterministic system is a system in which no randomness is involved in the development of future states of the system. A deterministic model will thus always produce the same output from a given starting condition or initial state.

The accurate timing for the transmission of scheduled Ethernet Frames requires dedicated circuitry like FPGAs such as the Zynq® UltraScale+™.

In industries that handle large amounts of big data from various devices, high data communication traffic can be a threat to real-time critical projects. Integration of TSN protocols into these systems ensures low latency for tasks such as synchronized measurements and embedded coordinated data logging. TSN provides scalability for any high-traffic system and protects your data communication systems for years to come.

Zynq supports 802.1bv, 802.1ch, 802.1bu/802.3br, 802.1Qcc, 802.1AS, 802.1Q, 802.1Qch, 802.1Qbv, 802.1Qav.



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Enhanced Cyber-Security - STIG/NISTIR 8259D COMPLIANCE

Secure Boot: Extension of the Root of Trust, prevents untrusted code execution and reverse engineering.

Secure OS: Hardened Linux Toolkit with the latest patches (Yocto) with admin control, password policies activated.

Secure Hardware: On Board TPM chip provides admin control of all interfaces and peripherals with encryption/activation.


More Information

Download Zynq One PagerZynq Datasheet

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